含独立源T-Π形电路等效变换的几个结论

本文讨论了含独立电源T形电路和Π形电路的等效变换,总结了几个相关的结论并给出了证明。这些结论扩展了T形电路和Π形电路等效变换的内容。通过实例说明了这些结论的正确性。本文的分析对电路课程教学具有一定的价值,可供教学参考。     

Single‐Stage ZVS‐PWM AC‐AC Power Converter Using All SiC Power Module for High‐Frequency Induction Heating Applications

This paper presents a novel prototype of a single‐stage zero voltage soft‐switching pulse‐width modulation ‐controlled ac‐ac converter with a silicon carbide (SiC)‐MOSFET/SiC‐SBD power module for high‐frequency (HF) induction heating (IH) applications. The newly developed ac‐ac converter can achieve higher efficiency than a Si‐IGBT/Si‐PN diode power module‐based prototype due to a low ON‐resistance of SiC‐MOSFET and a low forward voltage of SiC‐SBD under the condition of HF switching. The performances of the new prototype converter are evaluated by experiment with a single‐phase IH utensil of ferromagnetic stainless metal, after which the high‐efficiency and low switching noise characteristics due to the all SiC power module are actually demonstrated.     

PSO优化多核RVM的模拟电路故障预测

针对模拟电路健康管理的特点，提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征，计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值，将多个核函数线性组合，并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明，该方法在小样本情况下，预测效果优于单一核函数的RVM模型，适用于健康管理中实时预测，具有较好的实用性。     

“高频电子线路”理论课内嵌实验的探讨

国内大学的工程实践性课程通常理论课和实验课分开讲授，时间跨度大，内容不匹配，难以达到互相推动、互相促进的理想效果。在理论课讲授过程中同步内嵌实验课是一种无需变动复杂的课程体系，而能显著改善教学效果的方法。本文以“高频电子线路”课程的教学实践为例，探讨了此类改革面临的挑战和应对方法。     

Restraint Method for Overcoming Heating Irregularity and Improving Heating Equipment Efficiency for Beverage Cans Using High‐Frequency Induction Heating

We were able to reduce heating irregularities in equipment for heating beverage cans by using the high‐frequency induction heating method and determining the resulting improvement in the heating efficiency. The heating irregularity between the top and bottom of the can was reduced to less than 3°C by improving the arrangement of the heating coils for the beverage can by thinning the winding and changing the circuit configuration. The efficiency of power conversion was improved from 93.0% to 97.4%. In this paper, the configuration of the equipment and the experimental results are reported.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Fatigue life assessment of a low pressure steam turbine blade during transient resonant conditions using a probabilistic approach

This paper presents a sequential approach used in fatigue life prediction of a low pressure steam turbine blade during resonance conditions encountered during a turbine start-up by incorporating probabilistic principles. Material fatigue properties are determined through experimental testing of used blade material X22CrMoV12-1 along with statistical modelling using regression analysis to interpret the stress-life diagram. A finite element model of a free-standing LP blade is developed using the principle of sub-structuring which enables the vibration characteristics and transient stress response of the blade to be determined for variations in blade damping. Random curve fitting routines are performed on the fatigue and FEM stress data to ensure that the selection of the random variables used in fatigue life calculations is stochastic in nature. The random vectors are selected from a multivariate normal distribution. The use of confidence intervals in the probabilistic fatigue life model works effectively in being able to account for uncertainty in the material fatigue strength parameters and varying stress in the blade root. The predicted fatigue life of the blade is shown to be in good agreement with discrete life modelling results.     

Lower-error and area-efficient antilogarithmic converters with bit-correction schemes

In this article, we have proposed fast lower-error and area-efficient antilogarithmic converters. By employing new approximation schemes with two-region shift-and-add operations, our proposed converters can perform high-speed conversions from logarithmic numbers to binary numbers. Synthesis results show that our proposed converters can achieve time savings of over 32.5% and can save 42.3% of the area used compared with previously proposed methods. In addition, the percent error ranges for various logarithmic number system (LNS)-based operations used by our proposed logarithmic processor are lower than those of previous methods. Our proposed converters can be applied to LNS-based processors to ease the tremendous computation overhead and boost the performance.